library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.Achtung_const.all;

entity RAM_MUX is 
	port (
	row1,row2				: in unsigned(9 downto 0);
	col1,col2				: in unsigned(9 downto 0);
	com1,com2				: in std_logic_vector(1 downto 0);
	data_in1,data_in2   	: in RAM_Data;

	
	select1				: in std_logic;
	com					: out std_logic_vector(1 downto 0);
	row,col				: out unsigned(9 downto 0);
	data_out			: out RAM_Data			
	);
end entity;

architecture comp of RAM_MUX is
begin
	process(select1,row1,col1,com1,data_in1,row2,col2,com2,data_in2)
	begin
		if(select1 = '1') then
			row <= row1;
			col <= col1;
			com <= com1;
			data_out <= data_in1;
		else
			row <= row2;
			col <= col2;
			com <= com2;
			data_out <= data_in2;
		end if;
	end process;
end architecture;